1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device utilizing a capacitor as a programming element. More specifically, the present invention relates to the structure of a programming circuit in a dynamic semiconductor memory device including a memory cell having a capacitor.
2. Description of the Background Art
In a semiconductor device, programming circuits are employed for various applications. In a semiconductor memory device, for example, programming circuitry is employed for setting operation modes such as a fast page mode and an EDO (extended data output) mode, setting a word structure (xc3x978 or xc3x9716) and the like in a DRAM (dynamic random access memory). In order to finely adjust a resistance value for generating a reference voltage, a fusible link element is employed as the programming element.
In the semiconductor memory device, a defective address programming circuit for storing a defective address is employed in order to repair a defective memory cell. When a defective address is designated, an addressed normal memory cell is replaced with a redundant memory cell.
In such a programming circuit, a fusible link element (fuse element) is generally employed. An energy beam such as a laser beam is employed for programming (blowing/non-blowing) the fuse element. When such a fuse element is employed, a post-step of cleaning or the like is necessary for preventing blown fragments from scattering around the portion irradiated with the energy beam after blowing (laser blowing), resulting in a relatively long time for the program.
When fuse elements are arranged in high density in a high density/highly integrated semiconductor device, an adjacent fuse element is partially damaged due to misalignment of the laser beam, to cause difficulty in correct programming.
Further, the fuse elements to be blown are incompletely blown due to misalignment of the laser beam, to result in incorrect programming.
When the fuse elements are defective address programming elements for repairing defective memory cells, the number of the fuse elements to be blown is increased to result in a high possibility of erroneous programming. Such erroneous programming reduces the yield of the products.
In addition to the aforementioned fusible link elements, programming elements include an element called an anti-fuse. In this anti-fuse, a capacitor insulation film is subject to dielectric breakdown depending on information to be stored, for performing programming in accordance with conduction/non-conduction of the capacitor.
FIG. 35 schematically illustrates the structure of a conventional anti-fuse circuit. Referring to FIG. 35, the anti-fuse circuit includes a programmable capacitor (anti-fuse) 900 having an electrode node coupled to a node 902, a decoupling transistor 903 coupling a second electrode node of the programmable capacitor 900 to a node 904, an invertor 906 determining the program state of the programmable capacitor (hereinafter simply referred to as anti-fuse) 900 in accordance with the signal potential on the node 904 and outputting a signal FR indicating the result of the determination, a p-channel MOS transistor 908 charging the node 904 to the level of a power supply voltage Vcc in response to a trigger signal ZT, and n-channel MOS transistors 910 and 912 serially connected between the node 904 and a ground node. MOS transistor 910 receives a program signal AD at its gate, while MOS transistor 912 receives the signal FR outputted from invertor 906 at its gate.
The anti-fuse circuit further includes a p-channel MOS transistor 914 charging the node 904 to the level of the power supply voltage Vcc in accordance with the output signal FR from the invertor 906 and an n-channel MOS transistor 916 discharging the node 904 to the level of a ground voltage in accordance with a reset signal RST.
A high voltage (e.g., 12 V) is applied to the node 902 in a program mode, while the ground voltage is applied thereto in a normal operation mode (in a determination mode and in a standby state). MOS transistor 903 receives the power supply voltage Vcc on its gate and prevents the high voltage applied to the node 902 from being applied to the remaining circuit elements in programming of the anti-fuse 900. Operations of the anti-fuse circuit shown in FIG. 35 are now briefly described.
A programming operation for the anti-fuse 900 is described with reference to FIG. 36A. In the programming operation mode, the trigger signal ZT is set high and the MOS transistor 908 is held in a non-conductive state. The signal AD is set at a prescribed voltage level in accordance with programming information. Referring to FIG. 36A, the signal AD is set high in order to put (blow) the anti-fuse 900 in a conductive state. In an initial state, the node 904 is precharged to a high level and the signal FR from the invertor 906 is set low due to initialization of the trigger signal ZT. In response to the low-level signal FR, MOS transistor 914 is rendered conductive and the node 904 is held at a low level.
In the programming operation mode, the reset signal RST is set high and the MOS transistor 916 is rendered conductive. The node 904 is discharged to the ground voltage level and the signal FR rises to a high level. In response to the rise of the signal FR, MOS transistor 914 is rendered non-conductive while MOS transistor 912 is rendered conductive, and the node 904 is coupled to the ground node through the MOS transistors 910 and 912. While the reset signal RST is at the high level, the level of the voltage supplied to the node 902 is increased. Since the reset signal RST is at the high level, an increase of the voltage level of the node 904 due to capacitive coupling of the anti-fuse 900 is prevented when the voltage for the node 902 is raised, and the signal FR maintains the high level.
When the reset signal RST is set low, a high voltage for programming is applied to the node 902. A high voltage is applied across the anti-fuse 900 due to the voltage of the node 902, to cause a dielectric breakdown of a capacitor insulation film (the signal AD is at a high level). The voltage applied to the node 902 is transmitted to the node 904 to increase the voltage level thereat due to the dielectric breakdown of the anti-fuse 900. The voltage of the node 904 is determined by the ratio of the resistance of the anti-fuse 900 to the combined channel resistance of the transistors 910 and 912. When the voltage of the node 904 exceeds the input logic threshold voltage of the invertor 906, the signal FR lowers from the high level to a low level, the MOS transistor 912 is rendered non-conductive and the MOS transistor 914 is rendered conductive. The node 904 is charged to the level of the power supply voltage Vcc through the MOS. transistor 914. The decoupling transistor 903 transmits a voltage Vccxe2x88x92Vth, where Vth represents the threshold voltage of the decoupling transistor 903. Thus, the flow of a current from the node 902 to the node 904 through the anti-fuse 900 is cut off to complete the programming of the anti-fuse 900.
When the signal AD is set low in the programming operation mode, the MOS transistor 910 is held in a non-conductive state. When the node 904 is discharged to the ground voltage level through the MOS transistor 916 by the reset signal RST, the signal FR rises to a high level for driving the MOS transistor 914 to a non-conductive state. When the reset signal RST falls to a low level, therefore, all MOS transistors 908, 910, 914 and 916 are rendered non-conductive and hence the node 904 enters a floating state. When a high voltage for programming is applied to the node 902 in this state, the high voltage for programming is transmitted from the node 902 to the node 904 through the MOS transistor 903 by capacitive coupling though the anti-fuse 900. Thus, no high voltage is applied between the electrodes of the anti-fuse 900 and hence no dielectric breakdown is caused in the anti-fuse 900. In the non-blown state of the anti-fuse 900, the voltage level of the node 904 is increased due to the capacitive coupling of the anti-fuse 900, the signal FR from the invertor 906 falls to a low level as shown by the broken line, the MOS transistor 914 is rendered conductive, and the node 904 is charged to the level of the power supply voltage Vcc.
A stored information read operation is now described with reference to FIG. 36B.
When the trigger signal ZT is inactive, the reset signal RST is driven to a high level and the node 904 is discharged to the ground voltage level. The signal FR from the invertor 906 is responsively driven to a high level.
In the stored information read mode, the ground voltage is applied to the node 902 and the signal AD is set low.
When the trigger signal ZT falls to a low level in this state, the MOS transistor 908 is rendered conductive. When the anti-fuse 900 is in a conductive state, the current from the MOS transistor 908 is discharged to the node 902 through the anti-fuse 900, and the node 904 maintains a low level and the signal FR maintains the high level.
If the anti-fuse 900 is programmed in a non-blown state, the node 904 is charged to the level of the power supply voltage Vcc and the signal FR responsively falls to a low level when the MOS transistor 908 is rendered conductive. The information stored in the anti-fuse circuit is read based on the high or low level of the signal FR.
When the anti-fuse circuit is employed for specifying an operation mode, the signal FR is utilized as an operation mode specifying signal.
When the anti-fuse circuit is employed as a defective address programming circuit for repairing a defective memory cell, the signal FR corresponds to a defective address bit and a supplied address signal and the signals FR are compared with each other bit by bit, for determining whether or not any defective address is specified in accordance with the result of the comparison. A defective cell is replaced with a redundant cell or a normal cell is accessed on the basis of the result of the determination.
The aforementioned anti-fuse circuit, which is electrically programmable and does not require a laser beam or the like, is widely employed as a programming circuit for a high density/highly integrated semiconductor device.
The aforementioned anti-fuse circuit employs a capacitor. In order to program the capacitor, a relatively high voltage (e.g., 12 V) must be applied for causing dielectric breakdown. In order to apply the high voltage, it is necessary to sufficiently increase the breakdown voltage of a MOS transistor (insulated gate field effect transistor) forming a program control circuit for applying the high voltage. In a recent high-density/highly integrated semiconductor memory device, however, the MOS transistor is reduced in size as well as breakdown voltage. In order to apply a high voltage for programming, therefore, a MOS transistor having a higher breakdown voltage than in other peripheral circuits must be employed as a component, and hence the size thereof is increased (when a MOS transistor is formed along a scaling rule and a gate insulation film is increased in thickness, the size is proportionately increased in general). Thus, the area occupied by the program control circuit is disadvantageously increased.
U.S Pat. No. 5,110,754 discloses a structure employing a capacitor having the same structure as a three-dimensional capacitor of a DRAM cell as an anti-fuse in order to program a capacitor anti-fuse with no utilization of a high voltage for programming. In this prior art, a single capacitor is employed as an anti-fuse. When a single capacitor having the same characteristics as a memory cell capacitor is formed in a peripheral circuit region, however, no repetitive pattern in a memory cell array region is formed and hence the capacitor formed on the peripheral region is different in pattern and shape from the memory cell capacitor, to result in such a problem that it is difficult to form a capacitor for an anti-fuse having the same characteristics as the memory cell capacitor.
In order to read program information, a relatively large current must be fed through the anti-fuse (capacitor), and its electrode area must be sufficiently increased (for reading stored data at a high speed). Thus, the area occupied by the anti-fuse circuit is also disadvantageously increased, to impede a high integration.
An object of the present invention is to provide a highly reliable anti-fuse circuit occupying a small area.
Another object of the present invention is to provide a semiconductor device capable of utilizing a capacitor correctly having the same characteristics as a memory cell capacitor as an anti-fuse element.
Briefly stated, a semiconductor device according to a first aspect of the present invention includes capacitors, which are identical in pattern and structure to memory cell capacitors of a memory cell array, aligned along rows or columns and connected in parallel with each other for forming a single capacitor to be employed as an anti-fuse.
The semiconductor device according to the first aspect of the present invention includes a plurality of memory cells arranged in rows and columns, and each having a capacitor for storing information, a programming element having a plurality of capacitance elements aligned at least unidirectionally along the rows or columns, identical in structure to the memory cell capacitors and coupled in parallel with each other, and a program control circuit for programming the programming element by dielectric breaking down of the plurality of capacitance elements.
A semiconductor device according to a second aspect of the present invention includes a MOS capacitor formed by an insulated gate field effect transistor having a gate, and first and second impurity regions formed spacedly on a surface of a semiconductor substrate region with a space and connected with each other. The gate of the MOS capacitor is electrically connected to a conductive line through a contact hole formed on a channel region between the first and second impurity regions, the first and second impurity regions are coupled together to form a first electrode of the capacitor, and the conductive line forms a second electrode of the capacitor.
The semiconductor device according to the second aspect of the present invention further includes a program control circuit for applying a programming voltage between the first and second electrodes in a programming operation mode.
A semiconductor device according to a third aspect of the present invention includes a plurality of memory cells each having a capacitor for storing information, a programming element having a first programming capacitance element including a capacitance element having the same structure as the memory cell capacitor and a second programming capacitance element including a capacitance element having the same structure as the memory cell capacitor, and a program control circuit for serially connecting the first and second programming capacitance elements between first and second electrodes of the programming element in a normal operation mode while connecting the first and second programming capacitance elements in parallel between the first and second electrodes in a programming operation mode.
A semiconductor device according to a fourth aspect of the present invention includes a programming capacitance element having first and second electrode nodes and having high breakdown voltage and a low breakdown voltage depending on the polarity of a voltage applied between the first and second electrode nodes, and a program control circuit for applying a programming voltage to the programing capacitance element with voltage polarity providing the high breakdown voltage for programming the programming capacitance element in a programming operation node while applying a voltage to the programming capacitance element with voltage polarity providing the low breakdown voltage in a normal operation mode.
A semiconductor device according to a fifth aspect of the present invention includes a programming capacitance element having first and second electrode nodes and having a high breakdown voltage and a low breakdown voltage depending on the polarity of a voltage applied between the first and second electrode nodes, and a program control circuit for applying a programming voltage between the first and second electrode nodes with voltage polarity for the low breakdown voltage in a programming operation mode while applying a voltage between the first and second electrode nodes with voltage polarity for the low breakdown voltage in a normal operation mode.
A semiconductor device according to a sixth aspect of the present invention includes a programming capacitance element having first and second electrode nodes and having a high breakdown voltage and a low breakdown voltage depending on the polarity of a voltage applied between the first and second electrode nodes, and a program control circuit for applying a voltage between the first and second electrode nodes with the same voltage polarity in a programming operation node and a normal operation mode.
A semiconductor device according to a seventh aspect of the present invention includes a capacitor and a control circuit for applying a programming voltage to the capacitor to selectively cause dielectric breakdown in the capacitor in accordance with stored information in a programming operation mode while applying a one-shot pulse signal between capacitor electrodes in response to a state determination instruction signal for determining information stored in the capacitor in a determination mode.
A semiconductor device according to an eighth aspect of the present invention includes a plurality normal elements, a plurality of programming circuits each programmed of information for specifying a defective normal element by dielectric breakdown of a capacitor, and a plurality of redundant elements arranged in correspondence to a plurality of programming circuits and for replacing and repairing a defective normal element among the plurality of normal elements. The plurality of programming circuits and the plurality of redundant elements can repair a defective programming circuit and/or a defective normal element.
A plurality of capacitance elements identical in structure to memory cell capacitors are arranged in the same pattern as the memory cell capacitors. Also in a peripheral circuit region, therefore, the capacitance elements can be arranged and formed in the same pattern as the memory cell capacitors in a memory cell array, readily implementing capacitance elements having the same structure and characteristics as the memory cell capacitors. The memory cell capacitors are capacitance elements having excellent area utilization efficiency, and a programming element having a large capacitance value can be implemented with a small area.
In general, a memory cell capacitor has a breakdown voltage of half a power supply voltage, and dielectric breakdown can be caused with a low voltage by utilizing a capacitance element having the same structure as the memory cell capacitor as a programming capacitor (capacitor anti-fuse) while a low voltage can be employed as a high voltage for programming.
Further, dielectric breakdown can be reliably caused in a programming operation mode and a conductive/non-conductive (blown/non-blown) state can be reliably held in a normal operation mode by setting the polarity of the high voltage for programming and a voltage applied in the normal operation mode depending on the directionality of the breakdown voltage of the capacitor, implementing a highly reliable anti-fuse circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.